ESP32_RTOS_SDK V1.1.0

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i2s.h
1 /*
2 * ESPRSSIF MIT License
3 *
4 * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
5 *
6 * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP32 only, in which case,
7 * it is free of charge, to any person obtaining a copy of this software and associated
8 * documentation files (the "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
11 * to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all copies or
14 * substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #ifndef I2S_H
26 #define I2S_H
27
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31
48 //#define GPIO_PIN_REG_4 (PERIPHS_IO_MUX + 0x48)
49 //#define GPIO_PIN_REG_0 (PERIPHS_IO_MUX + 0x44)
50
51 #define TX_MASTER 0
52 #define TX_SLAVE 1
53 #define RX_MASTER 2
54 #define RX_SLAVE 3
55
56 struct sdio_queue {
57 uint32 blocksize: 12;
58 uint32 datalen : 12;
59 uint32 unused : 5;
60 uint32 sub_sof : 1;
61 uint32 eof : 1;
62 uint32 owner : 1;
63
64 uint32 buf_ptr;
65 uint32 next_link_ptr;
66 };
67
68 #define ETS_SLC_INTR_ENABLE() xt_ints_on(1 << ETS_SLC_INUM)
69
70 #define CONF_RXLINK_ADDR(addr) CLEAR_PERI_REG_MASK(I2SRX_LINK, I2S_I2S_RXLINK_ADDR);\
71 SET_PERI_REG_MASK(I2SRX_LINK, ((uint32)(addr)) & I2S_I2S_RXLINK_ADDR)
72 #define CONF_TXLINK_ADDR(addr) CLEAR_PERI_REG_MASK(I2STX_LINK, I2S_I2S_TXLINK_ADDR);\
73 SET_PERI_REG_MASK(I2STX_LINK, ((uint32)(addr)) & I2S_I2S_TXLINK_ADDR)
74
75 #define START_RXLINK() SET_PERI_REG_MASK(I2SRX_LINK, I2S_I2S_RXLINK_START)
76 #define START_TXLINK() SET_PERI_REG_MASK(I2STX_LINK, I2S_I2S_TXLINK_START)
77
87 void i2s_GPIO_init(uint8 mode);
88
98 void i2s_init(void);
99
109 void slc_init(void);
110
120 void slc_isr(void *para);
121
136 void create_one_link(uint8 own, uint8 eof, uint8 sub_sof, uint16 size, uint16 length,
137 uint32 *buf_ptr, struct sdio_queue *nxt_ptr, struct sdio_queue *i2s_queue);
138
146 void i2s_test(void);
147
156 #ifdef __cplusplus
157 }
158 #endif
159
160 #endif
create_one_link
void create_one_link(uint8 own, uint8 eof, uint8 sub_sof, uint16 size, uint16 length, uint32 *buf_ptr, struct sdio_queue *nxt_ptr, struct sdio_queue *i2s_queue)
Create DMA buffer descriptors.
slc_init
void slc_init(void)
DMA module initialization, including DMA mode and interrupt.
i2s_test
void i2s_test(void)
Functional DEMO for i2s module.
i2s_init
void i2s_init(void)
I2S module initialization, including FIFO, M/S mode, data format, clock frequency.
sdio_queue
Definition: i2s.h:56
i2s_GPIO_init
void i2s_GPIO_init(uint8 mode)
GPIO initialization, including config DATA, WS and BCK GPIO pin.
slc_isr
void slc_isr(void *para)
Process data received/treansmitted when interrupt occurs.