发现心仪岗位

The Opportunity

You will be the reason our chip is fast. You will write the hand-tuned kernels that power Large Language Models (LLMs) on our custom RISC-V hardware. You will work directly with hardware architects to exploit our proprietary Matrix (RVM) and Vector (RVV) extensions, squeezing every last FLOP out of the silicon.

Key Responsibilities

·Kernel Implementation: Write kernels for GEMM and common epilogues (bias/activation/quant); implement Softmax/RMSNorm; evolve toward attention kernels as the project matures.

·Micro-Optimization: Analyze assembly output. Did the compiler unroll the loop? Did we stall on a memory load? You fix it.

·Tiling & Layout: Calculate the optimal way to chop a large tensor into "tiles" that fit in our L1 cache/TCM.

·Benchmarking: Build the "speedometer" for the chip. Prove your kernel is faster than the baseline.

What We Will Teach You

·Our proprietary RVM (Matrix) and RVV (Vector) intrinsic APIs.

·How to use our cycle-accurate profilers and hardware counters.

·The specific memory hierarchy constraints of our AI SoC.

Must-Have Qualifications

·Strong C/C++ skills, specifically with a math/logic focus.

·Understanding of Computer Architecture basics: Registers, Cache Hierarchy (L1/L2), SIMD (Single Instruction Multiple Data).

·Comfortable reading/writing technical documentation (Instruction Set Architecture specs).

Nice-to-Have

·Experience with CUDA, OpenMP, or AVX/Neon intrinsics.

·Coursework in Linear Algebra or Numerical Methods.