Espressif Systems is looking for motivated semester interns to join us for a 6-month internship program in Singapore. This internship will provide hands-on experience in module-level and chip-level verification of wireless system designs. As an intern, you will contribute to building reliable and energy-efficient wireless SoCs and collaborate with design engineers to ensure design quality and accuracy.

Internship Responsibilities:

1. Assist in formulating verification plans for modules, establishing verification environments, and completing module-level and chip-level verification

2. Assist in executing regression tests to improve verification coverage

3. Support FPGA engineers and software engineers in completing FPGA prototype testing

4. Work with chip design engineers to identify and fix design defects

5. Ensure the integrity of chip designs and guide the design team in implementing a verifiable design process

Internship Requirements:

1. Bachelor’s degree or above in Electronic Engineering, Computer Engineering, or related fields

2. Familiar with Verilog and C/System Verilog verification

3. Skilled in scripting languages such as Python, Ruby, Shell, or Tcl

4. Familiarity with UVM is preferred; candidates with a foundation in OOP programming (e.g., C++, Java) are preferred.

5. Availability to commit to an internship duration of at least 6 months