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Job Title | classification | Job Type | Location | Posted | Apply | Job Number | Key Responsibilities | ||
---|---|---|---|---|---|---|---|---|---|
Physical Design Engineer |
Corporate | Apr 15, 2024 |
1255 |
10 |
Responsibilities 1. Be responsible for floor-plan layout, power network design, and CTS. 2. IR Drop analysis, DRC / LVS, RC extraction, etc. 3. Timing closure. 4. Area optimization. Qualifications 1. Bachelor’s degree, or above, in Microelectronics/Electronic Engineering/ Communications Engineering, or other related disciplines. 2. 6+ years of work experience. 3. Experience in PCB layout and tracing, using 40 nm techniques. 4. Ability to complete the whole P&R process and DRC, LVS, IR_Drop, STA, Low Power checks. 5. Familiarity with Tcl/Perl scripts and Verilog. 6. Familiarity with software tools for Design Flows and EDA delivered by Synopsys/Cadence. 7. Familiarity with Sign-off methodology and the EDA tools for STA/Power. |
recruit.sgpr@espressif.com | |||
Analog Design Engineer |
Corporate | Apr 12, 2024 |
1245 |
01 |
We are seeking a talented Analog IC Design Engineer who is passionate about cutting-edge technology and dedicated to producing innovative, high-quality work. As an Analog IC Design Engineer, you will be responsible for designing, simulating, and verifying complex analog circuits, such as high-speed SerDes, DDR, USB, or PHY applications. Responsibilities 1.Design, simulate, and verify cutting-edge analog circuits, such as high-speed SerDes, USB, ADDA, or PMIC, with an emphasis on innovation and quality. 2.Stay up-to-date with the latest research and trends in analog IC design and apply that knowledge to your work. 3.Guide the layout engineer in floor planning and layout improvement to ensure optimal performance and manufacturability. 4.Collaborate with application and product engineers and test engineers throughout the product development cycle to guarantee a successful product launch. Qualifications 1.Passionate about analog IC design and a keen interest in the latest developments in the field. 2.Minimum of 2 years of experience in transistor-level analog design, with a focus on high-speed SerDes, DDR, or RF PHY applications. 3.Experience in designing advanced analog blocks, such as op-amps, band-gaps, differential amplifiers, VCO, PLL, and DLL. 4.Experience designing SerDes block-level designs preferred, such as transmitter, high-speed VGA, CTLE, DFE, CDR, etc. 5.Understanding of signal integrity and noise analysis in high-speed wireline design preferred. 6.Expertise in full-custom analog layout techniques, including design, layout extraction, verification, and sign-off. |
recruit.sgpr@espressif.com | |||
ASIC Design Lead |
Corporate | Mar 23, 2024 |
4871 |
706 |
Espressif is seeking a talented ASIC Design Lead to join our newly set-up SoC team in Singapore. The building blocks in the SoCs we develop include DSP functions, CPU subsystems, and packet processing engines. This role focuses on the following: 1. Responsible for the architecture, design, integration, and verification of wireless communications SoCs. 2. Assist with the development of company documentation and generation of patents. 3. Involved in recruitment of talents to grow the team. 4. Mentor and develop the team to meet company’s strategic goals. Job Prerequisites: 1. Master’s degree in Electrical Engineering (or equivalent), with 8+ years’ industry experience. 2. Hands-on experience in RTL and verification, in-depth knowledge of mixed-signal SoC development cycle and best industry practices, from specification through tape-out and validation. 3. In-depth knowledge of SoC, embedded CPU and bus architectures, networking and control interfaces. 4. Proficiency in Verilog for RTL design and verification. 5. Confident user of C language and at least one scripting language (Python, tcl, Perl). |
recruit.sgpr@espressif.com | |||
Digital IC Verification Engineer |
Corporate | Jan 2, 2024 |
1251 |
07 |
Responsibilities 1. Develop verification programs and define the verification environment according to design documentation, in order to conduct module- to chip-level verification. 2. Perform regression tests to improve verification coverage. 3. Assist the FPGA and software teams in FPGA prototype testing. 4. Collaborate with chip design engineers to find and fix any design defects. 5. Ensure the integrity of chip designs by supervising the design department when building verifiable design processes. 6. Carry out door-level simulation, with UPF verification methodology, to ensure successful chip tapeout. Qualifications 1. Bachelor’s degree, or above, in Computer Engineering/Electronic Engineering/Communications Engineering, or other related disciplines. 2. 3+ years of work experience. 3. Familiarity with SoC and communication theory. 4. Familiarity with Verilog, proficiency in C/System Verilog verification. 5. Proficiency in Perl/Shell/Tcl scripts. 6. Experience in FPGA verification and/or chip tapeout is a plus. 7. Familiarity with VMM/UVM is a plus. |
recruit@espressif.com | |||
Digital Design Engineer / Lead |
Corporate | Jul 20, 2020 |
4701 |
503 |
Basic Qualications: 1. M.Tech/B. Tech in the field of VLSI/Electronics engineering. 2. Proficiency in System Verilog for RTL logic design and verification. 3. Experience in UPF based low power design flow. 4. EDA tool knowledge of Design Compiler, PrimeTime is preferred. 5. Automation skills in PERL and/or TCL and/or Shell is an added plus. 6. Team player,with good problem solving and communication skills. Job Description: 1. Digital IP design and SoC integration. 2. Perform Lint/CDC/LEC/Low-Power analysis at IP/SoC level. 3. Module level synthesis and timing constraints. 4. Must have worked on ARM/RISC-V CPU based designs. 5. Familiarity with FPGA/Silicon validation using C based tests and usage of standard debugging tools. 6. Familiarity with design of digital MAC/baseband/high-speed interface/CPU or DSP is a plus. Interpersonal Skills: 1. Energetic, self-motivated 2. Pro-active, oriented on execution 3. Attentive to details and quality 4. Team player 5. Good communications and reporting skills |
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Digital Verification Engineer / Lead |
Corporate | Jul 20, 2020 |
4702 |
504 |
Basic Qualification: 1. M. Tech / B. Tech in the field of VLSI/Electronics engineering. 2. Proficiency in UVM/SV and C/C++ based functional verification. 3. Experience in UPF based low power design verification. 4. Automation skills in PERL and/or TCL and/or Shell. 5. Team player, with good problem solving and communication skills. Job Description: 1. Drive functional verification at IP/SoC level using UVM/SV test bench. 2. Work closely with design team to define comprehensive feature test plans. 3. Perform functional and code coverage for logic verification sign-off. 4. Must have worked on ARM/RISC-V CPU based designs. 5. Must have performed gate level sim at SoC level. 6. Pre and Post-silicon debug/verification experience will be a plus. Interpersonal Skills: 1. Energetic, self-motivated 2. Pro-active, oriented on execution 3. Attentive to details and quality 4. Team player 5. Good communications and reporting skills |