Open Positions

Espressif is seeking a talented ASIC Design Lead to join our newly set-up SoC team in Singapore. The building blocks in the SoCs we develop include DSP functions, CPU subsystems, and packet processing engines.

This role focuses on the following:

1. Responsible for the architecture, design, integration, and verification of wireless communications SoCs.

2. Assist with the development of company documentation and generation of patents.

3. Involved in recruitment of talents to grow the team.

4. Mentor and develop the team to meet company’s strategic goals.

Job Prerequisites：

1. Master’s degree in Electrical Engineering (or equivalent),  with 8+ years’ industry experience. 

2. Hands-on experience in RTL and verification, in-depth knowledge of mixed-signal SoC development cycle and best industry practices, from specification through tape-out and validation.

3. In-depth knowledge of SoC, embedded CPU and bus architectures, networking and control interfaces.

4. Proficiency in Verilog for RTL design and verification.

5. Confident user of C language and at least one scripting language (Python, tcl, Perl).

Responsibilities:

1. Design, develop, and maintain digital signal processing (DSP) for wireless communications.

2. Code, simulate, and test solutions on field-programmable gate arrays (FPGA) and digital signal processors (DSP).

3. Lead work to test and validate to ensure system designs meet operational and functional requirements.

4. Solve problems concerning and provide support over the entire product lifecycle.

5. Research technology advances for potential application to company business needs.

Job Prerequisites:

1. Bachelor’s degree or higher in Electrical Engineering (or equivalent), with 5+ years DSP experience.

2. In-depth understanding of wireless technology, and digital/analog/RF communications.

3. DSP/Digital lab skills with oscilloscope, spectrum analyzer, digitizer, arbitrary waveform generator, synthesizer, etc.

4. Proficiency in Matlab, and in some or all of the following scripting languages: C, C++, Python.

Responsiblities:

1. Help define chip and block level specifications, and implement circuit designs topologies and architectures.

2. Perform Analog Spice behavior modeling and verification at both the transistor and top level.

3. Work closely with layout team and give support as needed.

4. Interface with test, product and application engineers to support the transition from prototype designs into mass production.

5. Author relevant technical documents and publications that describe the new circuit architectures and designs.

Job Prerequisites:

1. Master or PHD in Electrical Engineering (or equivalent)with expertise inanalog and mixed-signal IC design.

2. 5+ years of industry experience in transistor-level design of full-custom analog building blocks including but not limited to : amplifiers, active filters (continuous time & switched capacitor), oscillators, IO driver and ESD protection, power supplies (DC/DC Converters), ADC and DAC.

3. Master of at least one programming language, such as Python, MATLAB and C.

4. Proficiency in using analog design tools.

Responsibilities:

1. Plan, schedule, and carry out layout with quality and on time.

2. Utilize advanced CAD tools and mask design knowledge to deliver correct and robust layout.

3. Meet or even exceed engineering specifications and expectations by working closely with the circuit design teams.

4. Author relevant technical documents.

Job Prerequisites:

1. Bachelor in Electrical Engineering (or equivalent), with 5+ years analog/mixed-signal layout design of CMOS circuits.

2. Experience in layout designing of PA / LNA / PLL / ADC / DAC / VCO / TDC / phase interpolator / DCDC, etc.

3. Demonstrated expertise with custom and standard cell based floor planning and hierarchical layout assembly.

4. Knowledge of CADENCE layout tools.

5. Knowledge of Skill and Pcell.

6. Knowledge of at least one scripting language, such as Python, Perl,  Ruby.